MIT 6.828 JOS Lab 2 Report
MIT 6.828: JOS Lab
Assuming that the following JOS kernel code is correct, what type should variable
mystery_t x; char* value = return_a_pointer(); *value = 10; x = (mystery_t) value;
The type of
x will have to be
uintptr_t. Postulating that the code is correct, since the code snippet dereferences the pointer and writes to it,
return_a_pointer() can not return a physical address bypassing the MMU translation.
What entries (rows) in the page directory have been filled in at this point? What addresses do they map and where do they point? In other words, fill out this table as much as possible:
Entry Base Virtual Address Points to (logically): 1023 ? Page table for top 4MB of phys memory 1022 ? ? . ? ? . ? ? . ? ? 2
[see next question]
We have placed the kernel and user environment in the same address space. Why will user programs not be able to read or write the kernel's memory? What specific mechanisms protect the kernel memory?
What is the maximum amount of physical memory that this operating system can support? Why?
How much space overhead is there for managing memory, if we actually had the maximum amount of physical memory? How is this overhead broken down?
Revisit the page table setup in
kern/entrypgdir.c. Immediately after we turn on paging,
EIPis still a low number (a little over 1MB). At what point do we transition to running at an
KERNBASE? What makes it possible for us to continue executing at a low
EIPbetween when we enable paging and when we begin running at an
KERNBASE? Why is this transition necessary?
- Three major sections of the linear address space have so far been mapped: (1) the
pagesdata structure, (2) the kernel stack, (3) the space above
|Entry||Base Virtual Address||Points to (logically):|
||Page table for top 4MB of phyical memory|
||First page table of kernel|
||The kernel stack|
Isolation in the virtual address space is achieved by the permission bits of both page directory and page table entries. Those permission bits, located in the bottom 12 bits of every page table/directory entry, are checked by hardware.
To be more specific, pages are assigned either one of two privilege levels: supervisor or user. The current level is related to the CPL (current privilege level). A CPL of 0, 1 or 2 is equivalent to supervisor and a CPL of 3 is equivalent to user level. When executing in supervisor mode, all pages are accessible but when executing in user mode only other user mode pages are accessible.
4GB, which is the maximum number of bytes addressable using 32 bits.
(1) storing the page directory and page tables, (2) storing the pages array, and (3) having a chunk of memory under the kernel stack not mapped so as to trigger a page fault in case the stack goes over.
The transition to a high
EIPhappens with the jump to the
entrygdir.c, virtual address [0, 4MB) has been mapped to physical address [0, 4MB). Therefore, it is viable that we continue executing at a low
EIPafter enabling paging. The transition is necessary because the rest of the kernel is linked at high addresses.